/*
* Copyright (c) 2020 - 2024 Renesas Electronics Corporation and/or its affiliates
*
* SPDX-License-Identifier: BSD-3-Clause
*/

/**********************************************************************************************************************
 * File Name    : sysc_iobitmask.h
 * Version      : 1.00
 * Description  : IO bit mask file for sysc.
 *********************************************************************************************************************/

#ifndef SYSC_IOBITMASK_H
#define SYSC_IOBITMASK_H

#define R_SYSC_SYS_RAM0_ECC_VECCEN_Msk                      (0x00000001UL)
#define R_SYSC_SYS_RAM0_ECC_VECCEN_Pos                      (0UL)
#define R_SYSC_SYS_RAM0_EN_VCEN_Msk                         (0x00000001UL)
#define R_SYSC_SYS_RAM0_EN_VCEN_Pos                         (0UL)
#define R_SYSC_SYS_RAM0_EN_VLWEN_Msk                        (0x00000002UL)
#define R_SYSC_SYS_RAM0_EN_VLWEN_Pos                        (1UL)
#define R_SYSC_SYS_RAM1_ECC_VECCEN_Msk                      (0x00000001UL)
#define R_SYSC_SYS_RAM1_ECC_VECCEN_Pos                      (0UL)
#define R_SYSC_SYS_RAM1_EN_VCEN_Msk                         (0x00000001UL)
#define R_SYSC_SYS_RAM1_EN_VCEN_Pos                         (0UL)
#define R_SYSC_SYS_RAM1_EN_VLWEN_Msk                        (0x00000002UL)
#define R_SYSC_SYS_RAM1_EN_VLWEN_Pos                        (1UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Msk                    (0x00000001UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOP_Pos                    (0UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Msk                (0x00010000UL)
#define R_SYSC_SYS_WDT0_CTRL_WDTSTOPMASK_Pos                (16UL)
#define R_SYSC_SYS_I2C0_CFG_af_bypass_Msk                   (0x00000001UL)
#define R_SYSC_SYS_I2C0_CFG_af_bypass_Pos                   (0UL)
#define R_SYSC_SYS_I2C1_CFG_af_bypass_Msk                   (0x00000001UL)
#define R_SYSC_SYS_I2C1_CFG_af_bypass_Pos                   (0UL)
#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Msk           (0xFFFFFFFCUL)
#define R_SYSC_SYS_CA55_CFG_RVAL0_RVBARADDRL0_Pos           (2UL)
#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Msk           (0x000000FFUL)
#define R_SYSC_SYS_CA55_CFG_RVAH0_RVBARADDRH0_Pos           (0UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Msk                (0x00000007UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_BOOT_Pos                (0UL)
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Msk                (0x00000200UL)
#define R_SYSC_SYS_LSI_MODE_STAT_DEBUGEN_Pos                (9UL)
#define R_SYSC_SYS_LSI_MODE_STAT_SWD_JTAG_Msk               (0x00000400UL)
#define R_SYSC_SYS_LSI_MODE_STAT_SWD_JTAG_Pos               (10UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Msk                (0x00001000UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_CLKS_Pos                (12UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_OSCDRV_Msk              (0x0000C000UL)
#define R_SYSC_SYS_LSI_MODE_STAT_MD_OSCDRV_Pos              (14UL)
#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Msk                 (0x00000001UL)
#define R_SYSC_SYS_LP_CTL2_CA55_STBYCTL_Pos                 (0UL)
#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Msk                 (0x00000002UL)
#define R_SYSC_SYS_LP_CTL5_ASCLKQDENY_F_Pos                 (1UL)
#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Msk                 (0x00000004UL)
#define R_SYSC_SYS_LP_CTL5_AMCLKQDENY_F_Pos                 (2UL)
#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Msk                 (0x00000002UL)
#define R_SYSC_SYS_LP_CTL6_ASCLKQDENY_E_Pos                 (1UL)
#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Msk                 (0x00000004UL)
#define R_SYSC_SYS_LP_CTL6_AMCLKQDENY_E_Pos                 (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Msk          (0x00000002UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ASCLKQACTIVE_Pos          (1UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Msk          (0x00000004UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_AMCLKQACTIVE_Pos          (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Msk           (0x00000100UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PCLKQACTIVE_Pos           (8UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Msk          (0x00000200UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_ATCLKQACTIVE_Pos          (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Msk         (0x00000400UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_GICCLKQACTIVE_Pos         (10UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Msk        (0x00000800UL)
#define R_SYSC_SYS_LP_CA55CK_CTL1_PDBGCLKQACTIVE_Pos        (11UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Msk            (0x00000002UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ASCLKQREQn_Pos            (1UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Msk            (0x00000004UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_AMCLKQREQn_Pos            (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Msk             (0x00000100UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PCLKQREQn_Pos             (8UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Msk            (0x00000200UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_ATCLKQREQn_Pos            (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQREQn_Msk           (0x00000400UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_GICCLKQREQn_Pos           (10UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Msk          (0x00000800UL)
#define R_SYSC_SYS_LP_CA55CK_CTL2_PDBGCLKQREQn_Pos          (11UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Msk    (0x00000001UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_CA55_COREINSTRRUN0_Pos    (0UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Msk         (0x00000002UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQACCEPTn_Pos         (1UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Msk         (0x00000004UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQACCEPTn_Pos         (2UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Msk          (0x00000100UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQACCEPTn_Pos          (8UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Msk         (0x00000200UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQACCEPTn_Pos         (9UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Msk        (0x00000400UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQACCEPTn_Pos        (10UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Msk       (0x00000800UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQACCEPTn_Pos       (11UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Msk            (0x00020000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ASCLKQDENY_Pos            (17UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Msk            (0x00040000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_AMCLKQDENY_Pos            (18UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Msk             (0x01000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PCLKQDENY_Pos             (24UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Msk            (0x02000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_ATCLKQDENY_Pos            (25UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Msk           (0x04000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_GICCLKQDENY_Pos           (26UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Msk          (0x08000000UL)
#define R_SYSC_SYS_LP_CA55CK_CTL3_PDBGCLKQDENY_Pos          (27UL)
#define R_SYSC_SYS_GPREG_0_GPREG0_Msk                       (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_0_GPREG0_Pos                       (0UL)
#define R_SYSC_SYS_GPREG_1_GPREG1_Msk                       (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_1_GPREG1_Pos                       (0UL)
#define R_SYSC_SYS_GPREG_2_GPREG2_Msk                       (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_2_GPREG2_Pos                       (0UL)
#define R_SYSC_SYS_GPREG_3_GPREG3_Msk                       (0xFFFFFFFFUL)
#define R_SYSC_SYS_GPREG_3_GPREG3_Pos                       (0UL)

#endif
